# Verilog HDL Crash Course | Verilog Data Types | Module 03
## About
- Author: VLSI Excellence – Gyan Chand Dhaka
- Title: Verilog HDL Crash Course | Verilog Data Types | Module 03
- Tags: #articles
- URL: https://www.youtube.com/watch?v=ZC6iXtDyCdY&list=PLbZHjPJZbJ9UgVvJLQl7iSsU5GO3yJ7J_&index=4&pp=iAQB
## Highlights
a value of a wire can be read but not assigned to in a procedural block or in a function
- Note: Wires can't be assigned to in a procedural block!
e.g. always @
x <= y // x cannot be a wire! y can be though
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all the left hand side of expression in procedural block or in a function per always register data type
- Note: left hand side after initial and always of procedural blocks is a register type
e.g. always @
x <= y // x must be a register
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to model the latches flip-flops and memories we need to have a resistor type of data type but a register type of data type can also be used to model combinational circuits
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the input and in outputs are of type wire
- Note: Input and inouts must be of type wire
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the output keyword will be telling that this is the output port and it is at its data type so default data type if you don't declare it as a register then its data type default is going to be a wire but to override that we have to write we have to basically declare this as a register
- Note: module sample(a,b,c,d)
input a;
input b;
output c; // defaults to wire
output [2:0] d;
reg [2:0] d;
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