2022-11-12 17:59 Tags: # two-phase non-overlap clock Generating these signals shouldn't be done per [Dynamic Flip-Flop](Dynamic%20Flip-Flop.md). Make one circuit to serve many flip flops. ## Circuit  At its core a SR type D flip-flop. Driven by complementary signals. ### Analysing - Clk low: Output of top left NAND is high and hence $en1$ is low. That means $\overline{en_1}$ is high, which forces the bottom NAND output low. Thus $\overline{en_2}$ is low and $en_2$ is high. Since $\overline{en_2}$ is low, it will keep the top NAND output high even if the input to the system goes high - Clk goes low to high Forces one input to the bottom NAND low, hence $\overline{en_2}$ goes high after a delay determined by the even number of inverters in between. $en_2$ goes low shortly after this. Also when $\overline{en_2}$ goes high, both the top NAND inputs are high so the output is low, meaning $\overline{en_1}$ goes low after a delay determined by the even number of inverters. $en_1$ goes high shortly afterwards and ends the transition.  We can see that there is a time where $en_1$ is low ($\overline{en_1}$ is high) and $en_2$ is low ($\overline{en_2}$ is high). So driving the transmission gates will result in a complete disconnect in this period (aka dead-time or non-overlap) - Clk goes high to low Once $\overline{en_1}$ goes high, then $en_1$ goes low. $\overline{en_2}$ goes low after a short delay and then $en_2$ goes high. There is again a non-overlap period.  [^1] --- # References [^1]: [vr-4602-wk09-sc06-dynamicflipflop](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W9/vr-4602-wk09-sc06-dynamicflipflop.mp4)