2022-11-10 16:39 Tags: # hold time ## D Flip Flop ![](attachments/hold%20time-1.png#invert) The amount of time the data at the synchronous input must be stable after the active edge of the clock. [^1] --- # References [^1]: [IDC Online](https://www.idc-online.com/technical_references/pdfs/electronic_engineering/Setup_and_hold_time_definition.pdf)