2022-11-10 15:03 Tags: # current-starved inverter Take the inverter structure but connect the bottom end to the output side of a [Current mirror](Current%20mirrors.md) or a simple control voltage.  If the bias voltage is low - there isn't alot of current flowing into the NMOS branch so the high-low propagation delay is extended. There is no effect on the low high propagation delay in this topology. You could also add a PMOS above to slow both propagation delays. ## Output  Reducing the bias voltage:  [^1] --- # References [^1]: [vr-4602-wk09-sc02-gateusefunction](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W9/vr-4602-wk09-sc02-gateusefunction.mp4)