2022-11-10 16:37 Tags: # contamination delay The minimum amount of time from when an input changes to when the output starts to change. This is the absolute fastest a logic circuit will change. Every path from an input to an output has a contamination delay. Well-balanced circuits have similar speeds through a [combinational](Combinational%20and%20Sequential%20CMOS%20Logic.md) stage. ## Where to think about ### D Flip Flops If there are two D flip flops in series, the contamination delay of the first must be considered so as not to violate the hold time of the second flip flop. If there isn't enough delay from the output of the first flip flop to the input of the second, the input may change before the hold time has passed, contaminating the data. [^1] --- # References [^1]: [Wiki](https://en.wikipedia.org/wiki/Contamination_delay#:~:text=In%20digital%20circuits%2C%20the%20contamination,has%20reached%20a%20stable%20condition.)