2022-10-12 10:36
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# Two-stage op-amp circuit
High gain amplifiers are extremely important in electronics.
## Two-Stage Op-Amp
### Layout
[Differential Pair](Differential%20Pair.md), [Current mirror](Current%20mirrors.md) load and current source biasing.
[Common Source Amp](Common%20Source%20Amps.md) added to the [Differential Pair](Differential%20Pair.md) output. Bias using an active load, with the same bias voltage as the [differential pair](Differential%20Pair.md).
## Compensation
Will also need a compensation cap and res:
## Determining positive and negative input
E.g. right node increases, left decreases. Current in left increases, current in right decreases. $V_{o1}$ will decrease. The current to the CS reduces, which means the output voltage will increase as less current is pulled through the active load.
Thus the left input is minus and the right is plus.
## Gain of CS
Gain of CS is proportional to the output impedance - thus high gain means high output impedance. This means we can't drive a resistive load.
On chip you can get away with only driving capacitive loads. You could put a [Common Drain Amplifier](Common%20Drain%20Amplifier.md) at the output if needed.
## Complementary Circuit
## Nmos or Pmos Differential Pair?
Consideration:
- Input voltage range (asymmetrical - nmos towards VDD and pmos towards GND or VSS)
- Noise - PMOS tends to be better for overall noise (this can vary by process)
- Stability - n-channel common source tends to be better for stability
- PS type - larger the Vdd usually gives better performance, asymmetrical (Vdd and gnd) - problematic for 0V input like most analogue.
- Good to use GND as an analogue reference - no general solution.
- Not a decision made at op-amp level but at a system level
## Coupling
Because the transistors can match, it is common NOT to AC couple between stages (i.e. don't remove DC component of signals).
DC coupling - bias conditions for [Common Source Amp](Common%20Source%20Amps.md) needs to be well established.
For normal bias condition, $V_{i-}=V_{i+}$, the drain currents through M1 and M2 are the same. By symmetry, the voltage across both transistors in the current mirror would be the same. So we actually know what the gate-source voltage is and size the transistor appropriately.
We want **all transistors in saturation**.
### Saturation Conditions
M6: $V_{o2}<V_{DD}-|V_{eff,6}|$ (since pmos - take positive)
M7: $V_{o2} > V_{eff,7}\ (+ V_{SS})$
M3: $V_{DS,3}=V_{th,3}+V_{eff,3}$ which are given or chosen.
M1: $V_{DS,1}\geq |{V_{eff,1}}|$
The bias current of M1 doesn't change when we change the input voltage (to a first order) so the source-gate voltage of M1 is constant: $V_{sg,1}=|V_{th1}|+|V_{eff,1}|$.
Thus the voltage at the source end is $V_s=V_{i-}+V_{sg,1}=V_{i-}+|V_{th1}|+|V_{eff,1}|$
Thus if we vary the input up and down, the source voltage will vary by the same amount. Thus the drain votlage will change (since the voltage at the drain of M1 and M3, or $V_{d,3}$, is relatively constant).
So the min input voltage depends on the minimum voltage on drain-source 1.
## Common Mode voltage equations
Lower Input Voltage:
$V_{s,1}-V_{d,1} = V_{i-}+|V_{th1}|+|V_{eff,1}|-V_{th,3}-V_{eff,3}>|V_{eff,1}|$ or $V_{i-}>+V_{th,3}+V_{eff,3}-|V_{th1}| \approxeq V_{eff,3}$
Can almost reach the negative supply!
Upper Input Voltage:
Limited by M5 remaining in saturation.
As we increase the input voltage, the [differential pair](Differential%20Pair.md) source voltage increases and we squish M5 and eventually it will go out of saturation:
$V_{ds,5}= V_{DD}-V_{i-}-|V_{th1}|-|V_{eff,1}|\geq |V_{eff,5}|$ or
$V_{i-} <V_{DD}-|V_{th1}|-|V_{eff,1}|-|V_{eff,5}|$
Fair margin up to the positive power supply.
[^1]
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# References
[^1]: [vr-4602-wk05-sc01-opampcircuit](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W4/vr-4602-wk05-sc01-opampcircuit.mp4)