2022-11-10 15:08 Tags: # Tri-state Inverter Can't make with normal procedure since there should be a floating (high impedance) output state. ![](attachments/Gate%20use%20and%20special%20functions-4.png#invert) Inverter can be disconnected from PS and GND using enable signals. #### Truth Table ![](attachments/Gate%20use%20and%20special%20functions-5.png#invert) #### Alternative Circuit ![](attachments/Gate%20use%20and%20special%20functions-6.png#invert) We can swap the inverter and enabling transistors. Advantage: When in tri-state (high-Z), the capacitance at the output is lower. Disadvantage: Input connect closest to the output is the fastest input, thus it is a slower A-Y propagation delay. #### Sharing the Enable Often the inverter for enable is considered pat of the circuit, but it can be shared between many tri-state inverters. [^1] --- # References [^1]: [vr-4602-wk09-sc02-gateusefunction](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W9/vr-4602-wk09-sc02-gateusefunction.mp4)