2022-10-01 09:50 Status: # Tapeout Top level integration - connecting up all the blocks. You need a [floorplan](floorplan.md). ## Tape-out Check-list Key separate of I/C from discrete/PCB - no way to change when manufactured! No extra wire, buffer, need to completely respin the chip. Chip must be correct first time! Such an emphasis on simulation - be sure it works. ### Procedure - Design meets specifications? - Circuit is LVS clean? - DRC clean? - Corner simulations? Easy to be lazy but it would likely not work since parameters are not typical! - Monte Carlo sims of sensitive circuits? - Functional sims? - ESD in place? - I/O - input cells for input and output cells for outputs? - Sufficient test access? Can't observe anything on the chip if you haven't thought of it in advance (multiplexer so you can route different signals). - Proper layout - matching, power, clk, analogue and digital separate, no coupliong to sensitive nets - Pad location compatible with PCB and packaging. Make list comprehensive but concise. Put in the effort and do the work implied by ticking the box [^1] --- # References [^1]: [vr-4602-wk02-sc09-tapeout](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W2/vr-4602-wk02-sc09-tapeout.mp4)