2022-11-01 10:27 Tags: # Successive approximation ADC An algorithm for general purpose ADCs. ## Circuit Topology Sample and hold (need to use the input for a fairly long time) DAC - sample input voltage is compared to DAC output using a comparator. This drives a successive approximation register (a state machine that governs the algorithm). This SAR is clocked. Algorithm is a binary search.  ## Example Working - CK1: We get one bit of information comparing the input to $\frac{V_{ref}}{2}$. MSB=1 (retain it). - CK2: as per binary search, we break the next chunk in half and compare. Since the level is larger than the input, next MSB is set to 0. - CK3: divide range again, retain the next bit (input larger). - CK4: divide again, retain the next bit (input larger). All bits are exhausted, so output of ADC is the input of the DAC ($B_{out}$).  ## Disadvantages - Will need N-Clocks for an N-Bit converter (slower than flash, but still relatively fast) ## Advantages - Much less complex than flash converter since only 1 comparator. - Any ADC will work ## Charge Redistribution (DAC) in Successive Approximation ADC Small adjustments to the core DAC structure can be made. 1. Op amp has no feedback capacitor (doubles as a comparator) 2. Binary weighted capacitor array has one extra LSB 3. Instead of a reset phase, there is a sampling phase. ### Sampling Phases  Feedback engaged. 0V at the summing node. Input voltage sampled across all the capacitors. ### Capture Phase First open circuit the feedback to become a high-Z node.  Then switch all capacitors to the ground position in the sampling end. This puts -Vin on the summing node.  ### Binary Search Phase 1. MSB: Switch MSB to $V_{ref}$. Since MS Capacitor is equal to all the other capacitors (when in parallel, capacitance sums and we have included an extra LSB capacitor to make this work) this will cause a voltage change which is exactly half the voltage change at the bottom end of the capacitor. (i.e. 1/2 of $V_{ref}$). Thus the comparator compares $-V_{in}+\frac{1}{2}V_{ref}$ to 0V. The output is $Y_{N-1}= (-V_{in}+\frac{1}{2}V_{ref}<0V)$. $Y_{N-1}=1,\ V_{in}>\frac{1}{2}V_{ref}$ Thus the output of the comparator is the MSB in the conversion. 2. 2nd MSB: Put the MSB as per the algorithm into the right state. Then flip the second most significant bit. Voltage from previous comparison is kept at the same level, so voltage is the same as before plus the voltage change from the new bit. Since the capacitance is a quarter of the total capacitance, we'll get a quarter of the movement at the bottom end at the summing node, meaning the summing node has a quarter $V_{ref}$ added to it. $Y_{N-2}= (-V_{in}+\frac{1}{2}V_{ref}\cdot Y_{N-1}+\frac{1}{4}V_{ref}<0V)$ 4. so on for all the bits. ## Processing Positive and Negative Input Values Can change the reset and input phases for the MSB to obtain positive and negative sampling. [^1] --- # References [^1]: [vr-4602-wk07-sc06-adcsapprox](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W7/vr-4602-wk07-sc06-adcsapprox.mp4)