# Static RAM Cell Most generally useful is the static RAM. Core element: two back to back inverters. Value retained as long as the memory element has power. ![](attachments/Static%20RAM%20Cell.png#invert) Also has to be access to the memory element. ## Classical 6-transistor Memory Cell Access could be implemented as for the transmission gate based [Static Flip-Flops](Static%20Flip-Flops.md), but this would need 4 more transistors for access. By using the fact that PMOS pull up is weaker than NMOS pulldown, we can save 2 transistors (and get 25% more bits). Access point is 2 NMOS on either side of the inverters. The transmission of a zero through an NMOS is better than the transmission of a 1 through a PMOS. Thus if the memory element holds a 1, if we apply a zero to the bit line and access the word line ![](attachments/Static%20RAM%20Cell-1.png#invert) We can't really change this to a 1 but we can write a zero to the other side of the structure! We can only ever write zeros. ![](attachments/Static%20RAM%20Cell-2.png#invert) Since the NMOS is about 4x stronger than PMOS, we can probably make all transistors near minimum. ## Column Decoder If the memory size is not very big, a possible column decoder implementation is:![](attachments/Static%20RAM%20Cell-3.png#invert) Write operation (write is HIGH) - we enable a [Tri-state buffer](Tri-state%20Inverter.md) which drives the bitline, and the value comes from the databus. Then we drive $\bar{bit}$ line with the complementary write signal. If reading from the line, we need to disable the buffers so we can read the value from the buffers. This then drives the multiplexer using a [Tri-state Inverter](Tri-state%20Inverter.md) driven by $\bar{en}$ (i.e. write signal is low) [^1] ## Special SRAM Processes Since memory is so important, special SRAM processes have been developed with extra steps that enable us to make very large capacitance in a small area. ![](attachments/Static%20RAM%20Cell-4.png#invert) A deep trench is dug next to the access transistor which means you can have a very large capacitance but a very small footprint on the silicon. Should mention that this is not something you have access to in normal [Multi-Project Wafers (MPW)](Multi-Project%20Wafers%20(MPW).md). [^2] --- # References [^1]: [vr-4602-wk10-sc02-sramcell](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W10/vr-4602-wk10-sc02-sramcell.mp4) [^2]: [vr-4602-wk10-sc03-dramcell](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W10/vr-4602-wk10-sc03-dramcell.mp4)