2022-11-11 20:54 Tags: # Static Flip-Flops The core memory element in sequential digital logic. ## Master-Slave Architecture Use two [transparent latches](transparent%20latch.md) to form a master-slave edge triggered flip flop.  At the rising edge of the clock, the output from the master is transferred to the slave and that's when the output changes (not at any time). Thus this is a positive edge-triggered flip flop. ## Clock Implementation  We want a delay from slave latch to master latch because during the falling edge of the clock where the slave is going opaque and the master is going transparent, it is important that the slave goes opaque *before* the master goes transparent otherwise there might be leakage through the gate on the falling edge of the clock. ## NAND Based Flip Flop ### S-R Latch  Both HIGH: State is remembered. Illegal state is both of the inputs LOW. #### Truth Table  ### Gated SR Latch Create a delay type element - when ck is LOW, both $\overline{S}$ and $\overline{R}$ are HIGH, and the outputs are retained. When the clock is HIGH, both inputs are enabled so S becomes $\overline{S}$ and R becomes $\overline{R}$. ## D-type Flip Flop ### Simple Circuit  The input to the latch is a D-type signal so the set and reset is always complementary. This structure is used in discrete design but not ICs because it uses alot of transistors. ### Transmission Gates - Compact D Flip Flop Simplest static memory - back to back inverters. To write the state, we add transmission gates.  Master-slave structure then becomes  With the clock producing $\overline{en}$ and en. The capacitive load on the clock input should not be dependent on all the transmission gates, so inverters are used. It is possible to put in more inverters so the slave flip flop goes opaque before the master goes transparent (although this isn't really necessary in most cases). ### Advantages - Master flip flop uses only 8 transistors instead of 18! ### Timing Metrics for the Flip Flop  Time from the clock rising to the output changing is the sum of all delays through the clock then through the slave: $t_{pd}=t_1+t_2+t_3+t_4$ When the clock rises, the master goes opaque, meaning that to find the hold time conservatively, we need to find the time for the first transmission gate to go open circuit. Worst case for the first transmission gate is when the enable to the PMOS goes low, which happens after the delay through the two inverters. $t_h=t_1+t_2$ If the clock is low, the mater is transparent and if we change the input signal, we need it to make it all the way to the output of the second inverter in the master loop before we open the first transmission gate and close the second. Otherwise we won't have the right value in the memory element.  $t_{su}=t_5+t_6+t_7-t_1$ We subtract the first inverter in the clock because the clock will change the value of the input transmission after one delay, so we can change the clock a little sooner than we can allow the input transmission gate to go open circuit. ## Flip Flop with Set/Reset In many circuits it is necessary to know the intial state of a flip flop - e.g. MCU needs to know the initial value of the program counter. Same for state machines which need to know the startup state. Need a version of the flip flop where we can implement a set and reset. ### Easy Solve Replace inverters with NAND gates. Obtain active high SET and active low RESET. #### Set For slave forward NAND, if $\overline{SET}$ is LOW, the output is forced HIGH (asynchronous SET) - It is important to SET and RESET both slave and master (work on high and low clock) Since master/slave is in memory state, need to change this and you don't know which is in the memory state  #### Reset Active low reset. If auxiliary input is pulled low, the output becomes high and thus the output of the flip flop will go low.  You can only pull set or reset low at the same time otherwise the state becomes undefined. ## [Tri-State Inverter](Tri-state%20Inverter.md) based Flip Flop An inverter followed by a [Transmission Gate](Transmission%20Gates.md).  Then the flip flop becomes:  This design uses slightly more transistors than the transmission gate implementation but the delay doesn't depend on the drives input (since it doesn't go directly through a transmission gate). [^1] --- # References [^1]: [vr-4602-wk09-sc05-staticflipflop](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W9/vr-4602-wk09-sc05-staticflipflop.mp4)