2022-11-04 19:11 Tags: # Static CMOS Logic Gates Most versatile logic families in existence.  Pull up and pull down graph/network. Output is in the middle. Pull Up - Entirely PMOS devices. Pull down - Entirely NMOS. Reason: inputs swing from VDD to GND. If we try to pull the output of an NMOS to VDD, the output can be at most $V_{DD}-V_{th,N}$. The same is true for if we try to pull an output to ground via a PMOS.  So this is never done! ## Transistor Arrangement You can arrange the n-channel transistors in parallel or serial and this defines the logic function. ### Series - AND: If you put subgraphs in series, you have a connection if and only if both subgraphs have connection through them (this is a logic AND).  - OR: In parallel there is a connection if there is a connection through one, the other, or both.  ## Restrictions on Static CMOS Pull down - will be conducting when A is high or true. Can create a function connecting ANDs and ORs Since the pull down network pulls the output to ground and makes it FALSE, we have $Y=0\iff f(A,B,C,...,\cdot,+)$ We can use De Morgan's to find the inverse (swap AND for OR and invert all the literals). $Y=1\iff f(\bar{A},\bar{B},\bar{C},...,+,\cdot)$ CMOS can implement any function which is a combination of AND and OR with a final inversion. >IMPORTANT: It isn't possible to implement an AND or OR function in one CMOS gate using only the signals ($A,B...$) - it would have to be a NAND or NOR followed by an inverter. > >However, if signals and complements ($A,\bar{A},B,\bar{B},...$) are available then any function can be implemented! ## Example Function $Y=\overline{A\cdot B+C\cdot D\cdot(E+F)}$ ### NMOS Two parallel branches: Left Graph - A and B in series. Right graph - C and D in series with a parallel combination of E and F.  There are many ways to arrange these items, and this will affect the propagation delay. ### PMOS The two parallel graphs become two series graphs. The A and B graph is in parallel and the E & F branch becomes series in parallel with C and D.  ### Full Static Gate  ## Choosing Transistor Widths The next thing is to choose the sizes. As for the inverter, the channel length should be minimum. Widths has a number of approaches. ### Scaling to match the Pull-up or Pull-down resistance of an Inverter Assuming the current factor ratio is about 4, we choose k to be 2.  Thus we look at how many series devices are connected in one branch. The number of parallel devices is irrelevant - when the output changes it would normally be discharged through one branch only (due to a transition of one transistor causes the output to change state). Thus we need to scale the width by the number of devices in series (there are a few ways to do this, keep it simple).  ## CMOS for Driving loads Complex CMOS gates aren't as good at driving capacitance as inverters. Thus it is common not to have large capacitance at the output of CMOS gates and instead drive large loads with a buffer inverter. Thus having the same pull down resistance as an inverter may not be the best bet - scale to have the same input capacitance as an inverter! ## Scaling to match Inverter Input Capacitance Once you have identified the smallest transistor of this sizing, you can scale it down to being equal to an inverter. Internal propagation delay in the gate stays the same (since all values are scaled in proportion) but it becomes worse at driving external capacitance. This is usually a good tradeoff because the size of the gate decreases. Ex: the smallest width is 2, so 2/2=1. Thus scale everything down by 2:  ### Keep widths the same as in a unit Inverter This is usually done for the convenience of the layout although it gives poor performance. [^1] --- # References [^1]: [vr-4602-wk08-sc05-staticcmos](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W8/vr-4602-wk08-sc05-staticcmos.mp4)