2022-09-25 16:03 Status: # Silicon on Insulator Layered silicon-insulator-silicon substrate to reduce parasitic capacitance. ## Advantages - _Lower parasitic capacitance_ due to isolation from the bulk silicon, which improves power consumption at matched performance - _Resistance to [latchup](https://en.wikipedia.org/wiki/Latchup "Latchup")_ due to complete isolation of the n- and p-well structures - Higher performance at equivalent [VDD](https://en.wikipedia.org/wiki/IC_power-supply_pin "IC power-supply pin"). Can work at low VDD's (https://en.wikipedia.org/wiki/Silicon_on_insulator#cite_note-5) - Reduced temperature dependency due to no doping - Better yield due to high density, better wafer utilization - Reduced antenna issues - No body or well taps are needed - Lower leakage currents due to isolation thus higher power efficiency - Inherently [radiation hardened](https://en.wikipedia.org/wiki/Radiation_hardening#Physical "Radiation hardening") (resistant to soft errors), reducing the need for redundancy [^1] --- # References [^1]: [Wikipedia](https://en.wikipedia.org/wiki/Silicon_on_insulator)