2022-10-29 16:18 Status: # Sampling Process ## ADCs Sample and hold, ADC core, digital processor.  ## Sampling Offset Amplify the input signal without amplifying the offset. Set the input to zero with a switch then measure the output referred offset voltage.  ## CMOS Sampling Very easy to do. When you turn it off, the transistor is very high impedance so you can store a votlage signal on a capacitor. When switched on, the transistor has an on resistance but otherwise no voltage difference once the current has stopped.  Example: track and hold circuit. Must have a Vgs > Vth. This means that the input voltage can't be as high as the clock or it won't capture the whole signal.  Also, the finite falltime of the clock should be considered. Samples are taken on the low of the clock, thus there is a discrepancy in when samples are taken that depends on the input signal.   Thus we need a very fast clock edge and a stable clock with low jitter. ## Input Range Extension Add a PMOS to conduct high input voltages, and an NMOS for low voltages.  The bulk connections must be correct! If for ex the body of the PMOs connected to the source, the diode b/w drain and body could be forward biased. Also, the source may change. If the sample voltage is less than the input voltage when the transistor turns on, the NMOS source is on the sample side. If the sample voltage is higher upon turning, the source is on the input side (changed direction of current). You cannot actually tell which side is the source! [^1] --- # References [^1]: