2022-11-04 14:48
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# Propagation delay
One of the most important metrics for logic gates.
## Equivalent Model
## Simplified Model
We can ignore the input capacitance for finding the propagation delay (this will slow down the previous stage).
We can also lump the load capacitance and off capacitances together at the output.
Simple exponential rise/fall time.
Consider propagation delay to occur at the halfway point.
If $V_Y(t_{pd,LH})=\frac{1}{2}V_{DD}$ then $e^{\frac{-t_{pd,LH}}{\tau}}=\frac{1}{2}$
Thus,
$t_{pd,LH}=\tau\cdot ln(2)$
and similarly
$t_{pd,HL}=\tau_i\cdot ln(2)$
where $\tau_i=R_{ON,N}\cdot C_{L,tot}$.
## MOSFET Size vs. Power, Delay
Total capacitance is proportional to
$C_D=C_{OX}\cdot WL$, $C_G=\frac{3}{2}WL$ so $C_{L,tot}\propto WL$.
Since $R_{ON}=\frac{2L\cdot V_{DD}}{\mu C_{ox}W(V_{DD}-V_{th})^2}\propto \frac{L}{W}$ and thus $t_{pd}\propto R_{ON}\cdot C_{L,tot}\propto \frac{L}{W}\cdot WL\propto L^2$
Which is independent of the width!
For fast circuits, we need short channel lengths.
Recall the [CMOS Power Dissipation](CMOS%20Power%20Dissipation.md) is proportional to the switched capacitance, $P=f\cdot E_{DD}=f\cdot C_L \cdot V_{DD}^2\propto WL$ or the transistor area. Thus for small power, we should make the width small as well.
## Driving Large Capacitance
Large capacitances occur off-chip. You would need a much larger width in this situation.
## Simple Elmore Delay Model
You can look at the propagation delay at this network by looking at the time taken to travel from $V_A$ to $V_1$:
$V_A \rightarrow V_1:t_1=ln(2)R_1C_1$
$V_1\rightarrow V_2:t_2=ln(2)(R_1+R_2)C_2$
and so on.
Thus the total propagation delay is the sum of these delays:
$t_{pd}=ln(2)\left[ R_1C_1+(R_1+R_2)C_2+...+(R_1+R_2+..+R_N)C_N\right]$
## Formal Elmore Delay Model
Find the transfer function.
$\frac{V_N(s)}{V_A(s)}=\frac{1}{1+\alpha_1 s+\alpha_2 s^2+...+\alpha_N s^N}$
It can be proven that $\tau_{eq} =\alpha_1=\sum_k C_k\cdot R_k$ where $R_k$ is seen by the capacitor $C_k$ when $C_n,n\neq k$ is open.
The s factor (ignoring higher order) is our first order propagation delay and thus we can find the transfer function to be the following first order :
$\frac{V_N(s)}{V_A(s)}=\frac{1}{1+\tau_{eq}\cdot s}$
and thus $t_{pd}=ln(2)\cdot \tau_{eq}$
We use this for more complicated gates.
[^1]
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# References
[^1]: [vr-4602-wk08-sc03-cmosdelay](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W8/vr-4602-wk08-sc03-cmosdelay.mp4)