2022-11-09 11:26 Tags: # Preferred Gate In high performance circuits, it's best to think about the gates available in CMOS logic. ## Preferred Gate ### Comparing NAND and NOR NAND - series NMOS NOR - series PMOS  Scaling the widths to get the same on resistance as a unit inverter, we get:  ### Comparison - The NAND is 8 units wide vs. 10 for NOR - NOR has more capacitance in the pull up range NOR is not as good as NAND! Use NAND instead of NOR if you have a choice. ## Sum of Products Often comes out of a [Karnaugh map](Karnaugh%20map.md). Instead of implementing as AND with a summing OR gate, this can be implemented with [De Morgan's Principle](De%20Morgan's%20Principle.md).  ## Large Fan In Instead of implementing simply, we should now take this schematic and use deMorgans:  ## Performance Benefits Use the simple gates as often as possible. The reason is they are: - Smaller - Faster - Lower Power [^1] --- # References [^1]: [vr-4602-wk09-sc02-gateusefunction](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W9/vr-4602-wk09-sc02-gateusefunction.mp4)