2022-11-05 10:08 Tags: # NAND Gate Propagation Delay It is useful to consider the example in a NAND gate. ## N-Input NAND  $W_P=2W_{min}$ $W_N=W_{min}$ ### Propagation Delay Need to find the capacitance on the different nodes. If the drain capacitance on a minimum width device is $C_{D0}$ and the ON resistance for an NMOS is $R_{ON,N0}$. We have $2C_{D0}$ per PMOS (since they are twice the width) and $C_{D0}$ for the topmost NMOS.  so $C_{L,tot}=C_L+(2N+1)\cdot C_{D0}$ ### Propagation Delay for Rising Edge Fairly easy, just $t_{pd,LH}=ln(2)\cdot R_{on,PMOS}\cdot\Bigl(C_L+(2N+1)\cdot C_{D0}\Bigr)$ ### Propagation Delay for Falling Edge #### Transition on Topmost NMOS Consider a LH transition on the topmost NMOS, which causes the output to discharge to GND (i.e. all other inputs are high). This implies that all the other capacitances have been discharged to ground. $t_{pdHL,1}=ln(2)\cdot N\cdot R_{on,N0}\Bigl(\left( 2N+1\right)C_{D0}+C_L\Bigr)$ which expands to $=ln(2)\cdot N\cdot R_{on,N0}\Bigl( 2N^2C_{D0}+N\left(C_{D0}+C_L\right)\Bigr)$ >IMPORTANT: factor of N^2. Thus the delay is a poor function of fan in (number of inputs to the gate). >Also there is poor driving capability for the load capacitance (load will give a delay proportional to the number of inputs we have). #### Transition on Bottom-most NMOS Different propagation delay because all the intermediate capacitors have been charged to the output and these all need to discharge before the output changes. Using the [elmore delay model](Propagation%20delay.md#Simple%20ELmore%20Delay%20Model), the first time constant is the ON resistance for the bottom transistor times its drain capacitance, next is the ON resistance for the two bottom resistors times the next drain capacitance up and so on. $t_{pdHL,N}=ln(2)\cdot N\cdot R_{on,N0}\Bigl(C_{D0}+2C_{D0}+...+\left(N-1\right)C_{D0}+N\bigl(\left( 2N+1\right)C_{D0}+C_L\bigr)\Bigr)$ Which can be cleaned up using an arithmetic progression: $t_{pdHL,N}=ln(2)\cdot R_{on,N0}\Biggl(\frac{N(N-1)}{2}C_{D0}+ 2N^2C_{D0}+N\left(C_{D0}+C_L\right)\Biggr)$ $=ln(2)\cdot R_{on,N0}\Biggl(\frac{5}{2}N^2C_{D0}+N\left(\frac{C_{D0}}{2}+C_L\right)\Biggr)$ - This propagation delay also has a square dependency on fan in. - The delay from the bottom transistor has the delay from the top transistor *plus* a bit. This is a general result - propagation delay from a device sitting close to the output is shorter than a device sitting further from the output. - The fan in to a CMOS gate shouldn't ever be large. Limit it to 3 or 4 (except for special cases) otherwise it is too slow. ## N-Input NAND 2 $W_P=2W_{min}$ and $W_N=NW_{min}$ and $C_D=NC_{D0}$ $t_{pdHL,N}=ln(2)\cdot \frac{R_{on,N0}}{N}\Biggl(\frac{N(N-1)}{2}\cdot N\Bigl(NC_{D0}+ (2N+N)C_{D0}+C_L\Bigr)\Biggr)$ Collecting terms we get $=ln(2)\cdot R_{on,N0}\Biggl(\frac{N^2}{2}C_{D0}+\frac{5}{2}NC_{D0}+C_L\Biggr)$ We still have the square term (poor dependency on fan in) but it is smaller meaning faster. Still doesn't remove the issue of the square. We also see the factor N on the load capacitance has disappeared due to proper sizing. The top input is significantly faster when sized correctly. [^1] --- # References [^1]: [vr-4602-wk08-sc06-nanddelay](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W8/vr-4602-wk08-sc06-nanddelay.mp4)