2022-09-25 15:17 Status: # Multi-Project Wafers (MPW) For making cheap prototypes. ## Production Wafer vs. Multi Project Wafer Lots of instances scattered around. Instead, have multiple projects on the same wafer.  Main mechanism for test chips is MPW. ## MPW Service - Europractice - MOSIS ### Cost $/Area e.g. - $\$3000/$mm^2$ - 10-20 devices (chips) - Minimum Area - Technology choice, options ## 2019 Cheap: - 0.7$\mu m$ CMOS (on-semi): 300euro/$mm^2$, 5$mm^2$ min (5V) Expensive: - 22nm FD SOI (Global Foundries): 14k euros/$mm^2$, 9$mm^2$ min (0.8V - makes designs trickey, e.g. interface to LiIon) Prototyping is a few k$ to 100k ## Options - NMOS and PMOS transistors - Resistors - Capacitors - High voltage devices (20V, 100V) - 1.8V, 2.5V, 3.3V I/O ## Technology Generations Micron: 0.7$\mu m$: Cheap and Cheerful 0.35$\mu m$: 3.3V easy for analogue 0.18$\mu m$: (1.8V) analogue possible 130$nm$ - 90$nm$: (0.9V) analogue becomes difficult (I/O for analogue) - leakage starts to become an issue as the gate dielectric becomes so thin that the current just tunnels straight through it. Current flowing into the gate reduces the gain and becomes harder to use. Do you really need something that small? 65$nm$: stable digital 22$nm$: smallest you can commercially buy as an MPW. You get access to [Silicon on Insulator (SOI)](Silicon%20on%20Insulator.md) 10$nm$: FinFET - expensive 5$nm$: (smallest, not for mere mortals) [^1] --- # References [^1]: [vr-4602-wk02-sc05-MPW](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W2/vr-4602-wk02-sc05-MPW.mp4)