2022-11-16 10:41 Tags: # Memory Architecture Memory is a compact way to store information in electronic systems. - Store a large amount of data/information - Not always necessary to have simultaneous access to all this data. ## Example: MCU  Instructions could be in [RAM](Static%20RAM%20Cell.md) or [ROM](Read%20Only%20Memory.md). The instructions code needed is only one instruction per clock cycle for a single core - only need access to one instruction! Also only processing a small amount of data - need to access in a small way. This can increase the memory/reduce the physical size. ## Common Memory (RAM/ROM) Architecture To reduce size, arrange the memory bits into a 2D array.  Each block is a single bit of information. This needs a column and row decoder: If we have $2^m$ decoder for the rows, we can use m control lines to choose a row. Then the Column is a $2^n$ mux/demux for $2^n$ columns. This allows data to be piped in/out.  This gives us $2^{m+n}$ bits of memory but can only access one bit at a time. ### Operation Apply an address which selects the row. All of the memories sits at the input of the column decoder. The column decoder then chooses one of these to route to the data port on the memory. It is also possible to read out more than one bit simultaneously if you split the section in two, you could read one from each section (2-bit access). More common to parallel up these single bit access memory to the number of bits in your system (e.g. 64 bit OS). ## Access Structure Access point is called the word line (distributed across the cells) and when it goes high for instance all the cells read out/in their memories. The data port for each individual cell is called the bit line ( a shared wire) used to read out the data value. ## Number of Rows and Columns Usually similar number of rows and cols, so the area of the decoder will scale linearly with the number of cells, while the area of the memory cells will scale by the square of the number of rows. ## Area Thus the layout area of the bit elements dominates the overall area of the memory. Thus making each memory cell small gives us memory with a greater number of bits per unit area. This is true even if the memory element size decrease requires a more complicated row and column access. ## Row Decoder The typical row decoder is fairly straightforward. Conceptual setup:  Each AND gate has different address lines. [^1] --- # References [^1]: [vr-4602-wk10-sc01-memarchirecture](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W10/vr-4602-wk10-sc01-memarchirecture.mp4)