2022-10-30 10:56 Tags: # Low Offset Comparators Offsets in comparators can also be reduced by sampling methods. A comparator can be thought of as a gain element with a negative gain. If we look at how the op amp was offset compensated, we connected the output to the negative input and the samplednthe offset voltage across a capacitor.  Ck 1 disconnects first so we get a high impedance node sampling and holding the offset voltage on the cap. Then ck 2 disconnects from ground before the input is connected with ck3. IMPORTANT: The amplifying structure must be stable in feedback! Usually not normally imposed on comparators. Will essentially need to configure as an opamp with compensation internally for a multi stage comparator. For a simple single stage, we don't need to do anything (faster, not alot of gain). ## Advantages Compensation means it doesn't actually matter what the offset voltage is (might even be large!). Can drive ck2 transistor to an arbitrary reference: Vx See below the voltages during reset: The voltage across the capacitor is Vx-Vos.  When the input is applied, the input voltage is Vin +(Vos - Vx) - Vos = Vin - Vx. Thus we can compare the input to an arbitrary voltage **indepedent of what the offset voltage is**. ## Example: Common Source Amplifier used as a digital circuit  Interpret the output as a digital signal. ### Issues - Can still get charge injection (reduced by dummy switch or other usual means) - "Low" gain (low resolution). Solution: [Multi-stage offset compensation](#Multi-stage%20offset%20compensation) ## Multi-stage offset compensation  IMPORTANT: You can use a staged release of the stages to get a very low offset. When Ck 1 drops (opens the transistor), the input voltage of the first stage will decrease a little. Thus the output voltage will then increase by the charge injection on the input times the gain of the first stage.  The output referred charge injection will be sampled across the capacitor in the next stage. This means that if the reference voltage (Vx) is zero volts, at the output node. Imagine we have N stages with charge injection error of $\Delta V$ for each stage and a gain of $-g_m \frac{r_{ds}}{2}$since n and pmos. Then the procedural input referred chareg injection is the charge injection on the last stage divided by the gain of all the previous stages. Thus the input referred offset is $\Delta V_{in} = \Delta V_{final stage}/A^{N-1}$. This can be extremely small (as small as you like!). Total gain is $A_{total}=A^N$ which is very large. Since we aren't limited to negative feedback across the whole structure for stability, we can have as many gain stages as we like. ### Downsides Won't be as fast as a latching comparator due to increased capacitance with more stages (bandwidth drops), BW is approx inversely prop to number of stages. $\omega_{total} \approxeq \frac{1}{N\cdot \tau}$ where $\tau \approxeq \frac{r_{ds}}{2} \cdot C_{in}$ which will be subject to the Miller effect. Won't be super slow becaus we don't have compensation across the entire system. [^1] --- # References [^1]: [vr-4602-wk06-sc05-lowoffsetcomp](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W7/vr-4602-wk06-sc05-lowoffsetcomp.mp4)