2022-11-11 20:45 Tags: # Logic System Timing ## Mealy Machine Example  The clock period is from clock to output of FF's, logic propagation delay and the setup time for the flip flops. $T_{ck}=\frac{1}{f_{ck}}>t_{pd\ logic}+t_{pd\ FF}+t_{su\ FF}$ We can further see that the shortest propagation from the clock out of the flip flops (i.e. contamination delay of FF's) and contamination delay of the logic has to be longer than the hold time of the flip flops: $t_h<t_{cd\ logic}+t_{cd\ FF}$ We have no control over the contamination delays - if this is violated, the chip is broken! We might not even be able to test it (need to resimulate and respin a chip - expensive!) Always investigate hold time for digital logic! Usually hold times are violated because of clock skew between different flip flops: $t_h<t_{cd\ logic}+t_{cd\ FF}+t_{ck\ skew}$ [^1] --- # References [^1]: [vr-4602-wk09-sc04-logicdelays](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W9/vr-4602-wk09-sc04-logicdelays.mp4)