2022-11-10 16:31 Tags: # Logic Delays After logic function, [Propagation delay](Propagation%20delay.md) is the most important property of gates. ## Combinational Logic Delay Go from the 50% points for [Propagation delay](Propagation%20delay.md). The worst case- (longest) propagation delay is usually quoted and used to determine the highest clock frequency.  Delay through the block might be quite short! For multiple inputs, the propagation delay can be different for each. The shortest change through the block is called the [contamination delay](contamination%20delay.md), which can break the logic function by violating the [hold time](hold%20time.md). ## Example Circuit Two very different paths through the logic   ## Flip-flop Delays In sequential logic, the most common device is the edge-triggered D-type flip-flop. Propagation Delay - time it takes from rising edge of the clock till the output changes. Contamination delay - shortest time for propagation delay across [process variations](process%20variations.md).  For edge triggered - only time it matters is the rising edge of the clock. ### Setup Time However the input must be stable before the rising edge of the clock. If we denote the time the input is stable before the rising edge of the clock by t1. As t1 reduces, the propagation delay will increase and even further we may not even get a change at the output!  If we call the delay from clock rising edge to the output $t_0$, then plotting t0 vs. t1 looks like below:  Define the point where the slope is -1 and we can read the propagation delay and setup time for the gate.  Can also monitor this with simulations of t1 approaching zero. ### Hold Time We can move the edge change on the D-input on the other side of the clock edge and monitor what happens on the output.  t0 vs. t2 looks the same:  ### Worst Case Propagation Delay The worst delay found for either of these experiments. [^1] --- # References [^1]: [vr-4602-wk09-sc04-logicdelays](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W9/vr-4602-wk09-sc04-logicdelays.mp4)