2022-09-25 10:20 Status: # Layout Layers Layers correspond to the masks used in [fabrication](Fabrication%20Steps.md). All filled layers.  - N-Well: defining where [n-type](n-type.md) area goes. - Active layer: any transistor components (either gate or p/[n-type](n-type.md) junction or implant in the surface of the silicon) - N+select: [n-type](n-type.md) - P+select: p-type - Poly: (polycrystalline silicon) - for the gate - Contact: connection between metal 1 and silicon (hole in insulation layer - connection can be made to polysilicon and drain and source) - Metal 1: lowest metal layer (above the insulation) - Metal 2: Via 1 connects this to metal 1 - Metal 3: ... Special Layers: - Resistors (hi-Po high resistive poly resistors) - Capacitors (MiM - metal insulator metal) - transistors (low Vth, high V for (I/O)) [^1] --- # References [^1]: [vr-4602-wk01-sc09-layers](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W1/vr-4602-wk01-sc09-layers.mp4)