2022-10-28 18:00 Status: # Latching Comparators Use positive feedback. Keep all node impedances except 1 low to speed up the operating speed. Gain here is transconductance of the input [differential pair](Differential%20Pair.md) divided by the transconductance of the load pair (bottom right):  Could be a scale up in the current mirrors for further gain. Scale up of gain: cross coupled transistors!  Introduces positive feedback. Consider increasing positive and decreasing negative input at bias condition. Increased current through positive input fet and reduce current through left fet.  The increased current on the left output branch increases the voltage at that node. This is accentuated by the cross coupled fet, which has a decreased gate voltage which decreases the current flowing in it.  The output impedance is the transconductance of the [diode connected transistor](diode%20connected%20transistor.md) pair minus the cross coupled transistors:  $r_0=\frac{1}{g_{m2}-g_{m3}}$ implies that we can get a very large gain by having the gm's close together. Thus the overall gain of the circuit is thus given by: $A_v=g_{m1}\frac{1}{g_{m2}-g_{m3}}$ Die connected transistors on all the nodes implies the impedance on all the nodes is in the order of 1/gm so the comparator will be relatively fast. Can't go too greedy on the gain, because we will have latching in the comparator if gm3 is bigger than gm2. ## Managing Positive Feedback This can be fiddly. Embrace the positive feedback and make it very large (latching comparator). Back to back coupled inverters.  But you need a way to reset the state when biasing the latch at a trip point.  Need a way to apply an input signal (asymmetry). Different amount of current would cause the memory element to change state.  ### Advantages - Very High gain (near infinite) - Extremely fast (follow $V_{o1} = \Delta V_{in} e^{t/\tau}$ which is a positive exponential due to a pole in the positive plane due to positive feedback - extremely fast!) ### Disadvantages - Needs Reset (often okay - goes from analogue to digital and digital is normally clocked - only needs to be available on rising edge for example) - Offset is poor (due to use of transistors, partly addressed by using a pre-amp before the latching comparator) Very popular choice in high performance circuits. ## Example Implementation  Don't want a large current flowing through the inverter structure when drawing central nodes high so you put some nmos there to cut it off (connected to clk). Speed of the comparator is highly dependent on the capacitance seen at the output nodes.  It is custom to put a minimum size inverter so any routing capacitance doesn't apply to the node. Also the offset of the comparator also depends on the capacitance difference (good to have equal load). ### Circuit Walkthrough As the clock goes high, Vx1 and Vx2 will drop by the same amount initially and after a while the pull down on one node will be more than another - one will go down and another will go up to vdd. If vi2 is larger than vi1 then vx2 will be pulled down and thus will be pulled to ground.  Between each comparison the circuit has to be completely reset. If the starting point is not the same every time - it will be biased towards making the same decision it made last time and creates hysteresis in the circuit. ## Pre Amplifier to fix Kick-back Speed of the comparator means very fast transients - gate drain capacitance can easily influence the input. This is especially true for a high impedance input. For this reason (and offset) it is common to use a preamp (differential). Gain of 10 or so (can't have too much, because a large gain linear amplifier (which is needed) is slow).  [^1] --- # References [^1]: [vr-4602-wk05-sc06-latchingcomp](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W5/vr-4602-wk05-sc06-latchingcomp.mp4)