2022-11-04 16:12
Tags:
# Inverter Sizing
Since [propagation delay](Propagation%20delay.md) is a key metric for inverters, it is worth looking at sizing for minimum propagation delay.
Since most logic drives a few number of small gates, it is worth looking at inverters driving inverters driving etc.
Choose $L=L_{min}$
Since $R_{ON}=\frac{2LV_{DD}}{\mu C_{ox}W(V_{DD}-V_{th})^2}$
and the current factor for N and P are approximately related by $(\mu C_{OX})_N\approxeq 4|\mu C_{OX}|_P$
and $t_{pd}\propto R_{ON}\cdot C_{L,tot}$
## Issue
Since load capacitance is independent of rising or falling transition, choosing the same width of NMOS and PMOS means the rising propagation delay is 4x larger than the falling propagation delay.
## Potential Solution
- Increase the PMOS width to make the rising propagation delay smaller - but falling delay becomes larger as we add capacitance to the load.
This is not a good idea, as the logic depth is typically very large. E.g. between two flip flops the average propagation delay matters.
## Many Inverters
Minimise the input-to-output delay $\rightarrow$ minimise $t_{pdHL}+t_{pdLH}$
$C_{L,tot}=C_{DN}+C_{DP}+C_{GN}+C_{GP}$
Using
$W_P=kW_N$
Solve for k:
$C_{L,tot}=C_{OX}W_NL+C_{OX}kW_NL+\frac{3}{2}C_{OX}W_NL+\frac{3}{2}C_{OX}kW_NL$
$=C_{OX}W_NL\frac{5}{2}(1+k)$
Next, make a small assumption (for convenience) that the threshold voltage for the NMOS is the same as for the PMOS:
$V_{th,N}=|V_{th,P}|$
to express the on resistance as:
$R_{ON,N}=\frac{2LV_{DD}}{(\mu C_{ox})_NW(V_{DD}-V_{th})^2}$
$R_{ON,P}=\frac{2LV_{DD}}{|\mu C_{ox}|_P\cdot k\cdot W(V_{DD}-V_{th})^2}$
$R_{ON,P}=\frac{(\mu C_{ox})_N}{|\mu C_{ox}|_P}\frac{1}{k}R_{on,N}$
Thus,
$t_{pdHL}+t_{pdLH}=ln(2)\left[ R_{ON,N}\cdot C_{L,tot} +R_{ON,P}\cdot C_{L,tot}\right]$
$=ln(2)\cdot C_{OX}\cdot W_N\cdot \frac{5}{2}(1+k)\cdot L\cdot R_{ON,N}\left(1+\frac{(\mu C_{OX})_N}{k|\mu C_{ox}|_P} \right)$
We know that increasing the width for N and P doesn't change the delay (since capacitance increases but resistance decreases).
It is sufficient to find the minimum sum of propagation delays by finding the k to minimise the above expression.
$t_{pdHL}+t_{pdLH}=K\cdot (1+k)\cdot \left(1+\frac{(\mu C_{OX})_N}{k|\mu C_{ox}|_P} \right)$
$=K\cdot \left(1+k+\frac{(\mu C_{OX})_N}{k|\mu C_{ox}|_P} +\frac{(\mu C_{OX})_N}{|\mu C_{ox}|_P} \right))$
If k becomes very large, the propagation delay becomes proportional to k.
If k becomes very small, the $1/k$ term dominates.
This means that the propagation delay vs. k looks like:
$\frac{d(t_{pdHL}+t_{pdLH})}{dk}=K\left(1-\frac{1}{k^2}\frac{(\mu C_{OX})_N}{|\mu C_{ox}|_P}\right)=0$
Which produces the optimal current factor as
$k=\sqrt{\frac{(\mu C_{OX})_N}{|\mu C_{ox}|_P}}$
## Unit Inverter
$W_N = W_{min(layout)}$ and $W_P = k\cdot W_{min(layout)}$
## Scaled Inverter
For driving a large capacitance, it is customary to scale both the N and PMOS widths by the same factor 'S' ("strength" of the inverter):
## Driving Large Capacitance
Attaching a large capacitance to an inverter makes it very slow.
Instead have buffer stages; a chain of inverters of increasing size.
The total propagation delay through the stack will be the sum of propagation delays.
For fastest propagation delay, minimise all the propagation delays and set them equal.
### Input and Output Capacitance
$t_{pdm}=R_{ON,m}\cdot\left(C_{out,m}+C_{in,(m+1)}\right)\cdot ln(2)$
Since $R_{out}=\frac{K_1}{S}$,$C_{out}=K_2\cdot S$ and $C_{in}=K_3\cdot S$,
$t_{pdm}=\frac{K_1}{S_m}\cdot\left(K_2\cdot S_m+K_3\cdot S_{(m+1)}\right)\cdot ln(2)$
$=K_1K_2+K_1K_3\frac{S_{(m+1)}}{S_m}$
Where $K_1K_2$ is the intrinsic or unloaded propagation delay of the inverter (which is the bare minimum - can't get better than this).
For the shortest delay we require that $\frac{S_{(m+1)}}{S_m}=constant=A=\sqrt[N]{\frac{C_L}{C_{in,1}}}$
Thus if we begin with an inverter of size $S=1$, then $S=A$, then $S=A^2$ and so on to $S=A^{N-1}$.
The optimal value for A can't be found mathematically, but it's from 3-6.
Try to keep A < 10 (for very large capacitances and good power).
[^1]
---
# References
[^1]: [vr-4602-wk08-sc04-invertersize](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W8/vr-4602-wk08-sc04-invertersize.mp4)