2022-09-21 11:34 Status: # Fabrication Steps ## CMOS Inverter Example Start with P substrate - Put down an n-well for p-type transistors ![](attachments/Pasted%20image%2020220921114201.png#invert) - Then remove photo resist Then put down photoresist where transistors are etch away Fill with [Field Oxide](Field%20Oxide.md) insulator. ![](attachments/Pasted%20image%2020220921114307.png#invert) Next step is tricky (gate oxide) Grow thin (1nm) gate oxide across the whole wafer ([Furnace](Furnace.md)) - Be careful it doesn't get contaminated ![](attachments/Pasted%20image%2020220921114426.png#invert) Then deposit polycrystalline silicon which is highly doped (used as gate material) ![](attachments/Pasted%20image%2020220921114444.png#invert) This becomes the gate electrodes. Now etch away bits of polysilicon we don't want. ![](attachments/Pasted%20image%2020220921114528.png#invert) Then put down source and drain implants. Commonly use gate as a shield - ensure it is perfectly aligned for performance. ![](attachments/Pasted%20image%2020220921114748.png#invert) Then do the same for the p implants using [Ion implantation](Ion%20implantation.md) ![](attachments/Pasted%20image%2020220921114809.png#invert) Then strip the photoresist - [anneal](Furnace.md#Annealing) to reconstitute lattice. Then do the interconnects - lay down material with [Chemical Vapour Deposition](Furnace.md#Chemical%20Vapour%20Deposition) then etch holes where you want connections ![](attachments/Pasted%20image%2020220921115033.png#invert) Then put metal on with [Sputtering](Sputtering.md) and etch away what you don't want. ![](attachments/Pasted%20image%2020220921115104.png#invert) Can have 8-10 metal layers (Oxide then metal repeated for complex interconnections). ![](attachments/Pasted%20image%2020220921115148.png#invert) --- # References [^1]: [vr-4602-wk01-sc08-fabsteps](attachments/Lectures/W1/vr-4602-wk01-sc08-fabsteps.mp4)