# Dynamic RAM Cell If we relax the requirement that memory cells should retain memory when powered (see [Static RAM Cell](Static%20RAM%20Cell.md)) we can fit in more memory cells (bits)! ## Circuit  Memory element is a capacitor on which a charge is stored. There is a single transistor used to access the capacitor. When the word line goes high, the capacitor is switched onto the bitline and the voltage on the cap is transferred to the bit line. We can fit nearly 3x more bits compared to [Static RAM Cell](Static%20RAM%20Cell.md). ## Challenges Want to fit a large number of cells to each bit line, and because of the capacitance of each access transistor, they will add up and give a large parasitic capacitance. The size of the memory capacitor won't be very big to reduce the area.  The voltage on the bit line when the word line has activated will be divided down. ### Charge Conservation  Total charge when wordline is low: $Q_1=V_H\cdot C_M$ and $Q_2=V_{bit}\cdot C_{bit}$. When the wordline goes high, the voltage on the memory element is the sum of charges divided by the total capacitance: $V_{H2}=V_{bit2}=\frac{V_H\cdot C_M+V_{bit}\cdot C_{bit}}{C_M+C_{bit}}$But since $C_{bit}>>C_M$, this becomes $V_{bit2}=V_H\frac{C_M}{C_{bit}}+V_{bit}\left(1-\frac{C_M}{C_{bit}}\right)$ So the change in the bitline voltage is $\Delta V_{bit}=V_{bit2}-V_{bit}=\left(V_H-V_{bit}\right)\frac{C_M}{C_{bit}}$ ### Detecting Voltage Change It is custom to precharge the bitline to half the logic voltage stored on the capacitor. Thus the voltage on the bitline looks like this:  These voltage changes ($\Delta V_{bit}$) are nowhere near a decent logic level so we need to do something before reading. ### Restrictions Also to read out/in, we need the voltage in the word line to be higher than the threshold voltage and a little higher than the voltage we want to store as a high on the capacitor. Either: - Use VDD for the memory, meaning we have to generate $V_{word}>V_H+V_{th}+V_{eff}$ - Use $V_H < V_{DD}$ (lower power implementation) ## Other Issues Readout destroys the stored value. A high stored on the capacitor is translated into half of a logic high (nearly as low as it is high). ## Access Strategies ### Folded Bitline (for differential readout) Do a differential measurement of the logic levels. Slight rearrangement of RAM needed - only half of the positions are occupied by memory cells, while the others are left blank. NB: Even if it looks like it is half occupied, you can place elements into the free space (thus no wasted area on the chip). #### Setup Core idea is that when wordline 0 is high, a charge is dumped on that line. We can measure that change with respect to bitline 1. This can be applied to the other lines, e.g. 0 and 1,2 and 3 etc.  #### Recovering Bitline Logic Levels Use a [Sense Amplifier](Sense%20Amplifier.md) which connects to two bitlines. Two back to back inverters act like a latching comparator. Additionally, there are two transistors used to precharge the bitlines to half the logic high level.  Prior to a readout, both the lines are precharged to $V_H/2$. When the wordline is activated, the sense amplifier is put into action by enabling the power supplies and it will amplify the difference in bitline voltages. #### Operation Looking at bitline voltages as a function of time: - First precharge is high, which then goes low when the voltages reach $V_H/2$. - Then the wordline changes (no effect on bit1, bit1 goes higher or lower depending on a 0 or 1 on the memory element) - Then latch is driven high when the bitline has been read out from the word line. Latching will happen. If bit0 is larger than bit1, then bit0 is pulled to VDD and vice versa (see [Latching Comparators](Latching%20Comparators.md) for this operation). - Once the logic levels have been captured it is possible to start a new cycle.  This ensures that logic levels are amplified and the logic levels are rewritten into the storage element as long as the wordline is kept high. #### Reading Thus readout is no longer destructive and actually acts as a refresh of the memory. Since the bit is stored on a capacitor, due to the reverse leakage in the diodes connected to the NMOS the memory will eventually leak away (hence the name dynamic memory). Thus a routine read of all bits is required to retain memory. This makes DRAM more complicated to use as this system to keep accessing all word lines must be implemented. #### Sense Amplifier Capacitance on bit0 and bit1 lines are essentially the same. That means that the comparator is not biased towards flipping one way or another (very important for the folded bitline!). It means we can attach more bits (very symmetrical) and thus get better resolution. A lower offset in the comparator allows us to resolve smaller differences in between the high and low state so we can add more bits to the lines (i.e. larger $C_{bit}$ capacitance). #### Sense Amplifier This circuit is typically used in other memories ([Static RAM Cell](Static%20RAM%20Cell.md), [Read Only Memory](Read%20Only%20Memory.md)) as it is so useful in speeding up the readout process! ## DRAM Capacitor Implementation Determines how many bits you can have. Larger C means more bits (deal with a larger parasitic capacitance on the bitline). In CMOS, the largest capacitance you can get is the [gate capacitance](MOSFET%20Capacitances.md). That means that memory element is typically implemented as another NMOS with the gate tied to VDD. The gate-source capacitance is used as the memory element. We go to VDD so we only need NMOS in the memory element which means it can be more compact (no n-well to NMOS transistor spacings).  [^1] --- # References [^1]: [vr-4602-wk10-sc03-dramcell](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W10/vr-4602-wk10-sc03-dramcell.mp4)