2022-11-12 17:45 Tags: l# Dynamic Flip-Flop Can be made smaller than [Static Flip-Flops](Static%20Flip-Flops.md). ## Dynamic Latch Relies on the parasitic capacitance sitting on the input as the memory element.  To write the memory element, we use a [Transmission Gate](Transmission%20Gates.md).  The presence of parasitic diodes in the transmission gate will discharge the capacitor, meaning the memory will decay over time. It is unknown which of the reverse currents in the NMOS or PMOS is larger so looking at the memory voltage (Vx at the input of the inverter). There is a jump due to charge injection when enable is changed, then the level may decay (we forget the value). When enable goes high again, the input is connected to the capacitor.  If being pulled to GND, the NMOS leakage is larger than the PMOS. Vice versa is true for being pulled to VDD.  The drift could also go towards the middle of the supply. We can only retain a good logic level for a certain amount of time ($t_{retain}$). This gives us a minimum frequency (or maximum period) - typically in $\mu s$.  ## Dynamic Flip-Flop  To ensure there is no bleed through from D to Q on the falling edge of the clock, it is common to use a [two-phase non-overlap clock](two-phase%20non-overlap%20clock.md) system. The complementary enable signals are  This structure guarantees there is not a direct path from the D to Q. ## Advantages of Dynamic Flip-Flop - There are only 4 transistors - smallest we can make a flip flop! - Small - Fast - Low Power ## Downsides - Minimum frequency to be clocked (non-static) [^1] --- # References [^1]: [vr-4602-wk09-sc06-dynamicflipflop](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W9/vr-4602-wk09-sc06-dynamicflipflop.mp4)