2022-09-28 09:37 Status: # Digital Tools Programming language where you specify how components are connected or their function. ## Main Languages VHDL/Verilog - Complex digital synthesis - behavioural modelling - also analogue but not as popular now ## Verilog-A and AHDL Simulating a chip in spice is impossible - for a digital chip you don't need spice (too detailed). Need RTL level. Analogue and digital - need to know interface works so crude analogue is fine (behavioural). ## Mixed Simulation - Verilog/VHDL for digital - SPICE for analogue (not too complex analogue) ## Digital Synthesis - Synthesis to technology - FPGA (can change) - ASIC (can't change) - Can make a late decision about what part of the system goes on the [ASIC](ASIC.md) and what on the [FPGA](FPGA.md) - Synthesis using library components - NAND, NOR, flip-flops, inverters, buffers - can be more complicated - e.g. FPGA adders, multipliers, CPU cores else basic components in standard set - Special IP Macros - e.g. RAM, CPU, USB interface (alot of effort - not what you want to do) - Instead buy from someone (vendor gives you the layout and a simulation interface). - Very popular - e.g. ARM core CPU used in alot of places. - Gate delays and wire delays (only fully known when gate is wired up) - Extractions/post layout simulations ## Standard Cells Not commonly used for analogue functions - digital is standard. - NAND, NOR, flip-flops, inverters, buffers Variations: - fan in (number of inputs), fan out (drive a certain size capacitance - large driving nand gate would have a large input capacitance). - Reset/preset - Typical key features - Same height for efficient stacking - abutment connection of power supply so you can place the blocks directly next to each other - not excplicitly routed. -  - Standard port placement (metal 1 is horizontal - metal 2 in ports, only metal 1 and poly in the chip if possible in the technology)  - Analogue - Opamps - ADC - Voltage references ## Place and Route Placed directly next to each other so Vdd and Gnd are next to each other. Gaps between rows - put in filler cells (power supply decoupling).  ### Manhattan routing Don't get into any crowding ## Channel Routing Used for not many metal layers  ## Area Routing If lots of metal layers - do all routing on higher metal layers which aren't used inside the cells.  ## Place then route vs. Place & Route Combined Delay determined by length of wires so you don't actually know the fan out until you route it - combined place and route is used for more expensive (smaller) processes. [^1] --- # References [^1]: [vr-4602-wk02-sc08-digitaltools](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W2/vr-4602-wk02-sc08-digitaltools.mp4)