2022-10-05 09:33 Status: # Digital MOSFET Model Normal MOS model is way too detailed and complicated to use for digital analysis - really you only care about propagation delays. ## Simplified Transistor Model VGS (gate voltage) is usually either low(VSS/GND) or high (VDD). Turn the drain current into a linear model:  Either turned off or a resistor - on resistance.  > This model always underestimates the current (meaning our speed measurements will be overestimates - a good thing!) ## Simplified Capacitive Model For a digital circuit, transistor will spend most of its time in the triode region, where the channel is wide open. So we assign half the gate-channel capacitance to source and drain. i.e. $C_{gs}=C_{ds}=C_{OV}W+\frac{1}{2}WLC_{OX}$ in the triode region. Almost all logic sits in inverting structures.  A rising edge at input becomes a falling edge at the output. Thus voltage change across the capacitor is 2VDD.  By Millers theorem, we can move the capacitance $C_{gd}$ to two capacitances of twice the value (simple gain of -1).  We can ignore the bulk drain capacitance. Also, we can assume that the capacitors are grounded (even though the source is unlikely to be grounded) and this is sufficiently accurate. ## Complete Digital Model  Equations ignore the overlap capacitance - slight overestimate.  NFET, PFET models are identical (with different parameter values). [^1] --- # References [^1]: [vr-4602-wk03-sc06-digitalmodel](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W3/vr-4602-wk03-sc06-digitalmodel.mp4)