2022-11-04 09:50 Tags: # Digital CMOS Voltage Transfer Characteristic (V.T.C) Very similar VTC to CMOS inverter. ## Inverter PMOS connecting output to positive supply. NMOS connects the output to ground (or Vss). The gates are connected together. ## Ex: NAND Gate For a NAND, we can think of the independent inputs as changing at different times (e.g. A and B). e.g. B high, A low produces:  Thus understanding the inverter helps us understand any static CMOS gate. ## Voltage Transfer Characteristic of CMOS Inverter When input voltage to the inverter is below the threshold voltage of the NMOS, only the PMOS is on (in triode since there is zero current flowing in it but the transistor is on) and the output is connected to VDD directly.  Once the input reaches the NMOS threshold voltage, the NMOS will start to draw current. PMOS voltage small so still in triode, NMOS in saturation due to large voltage across it.  At some point the NMOS and PMOS are both in saturation. This is the steepest point of the VTC and corresponds to the highest gain of the inverter (typically -10 to -100 small signal gain). Eventually the PMOS enters saturation and NMOS enters triode (nmos will have lower voltage across it).  When the gate-source voltage of the PMOS is less than the threshold voltage, the NMOS remains in the triode region but the voltage across it would be zero.  ### Current through the inverter transfer characteristic. Peak current obtained when both devices are in saturation. Current follows a square law when one is in triode and the other is in saturation.  ## Inverter Design Considerations The design can choose where the transition region lies. It has to lie between the N threshold and VDD+Vpth but you can move it left or right depending on the aspect ratio of the transistors involved. E.g. make the NMOS wider - conducts the same saturation current as the pmos with a lower gate voltage. This shifts the characteristic to the left. Thus current peaks at a lower input voltage and to a higher value:  Exact point of transfer is often not important for a digital input (e.g. GND or VDD) however translating between different levels means this can be important! ## Noise Margins Can be defined by looking at the transfer function. ### Simple Definition Look at the two points where the slope is -1, we can define the output high voltage as the top value and the output low voltage as the lower point. Similarly, looking at the input voltage when the slope is -1, if the input is lower than a this voltage we can guarantee that the output is higher than $V_{OH}$. Also if the input is larger than the point where the slope is -1 then we know the output will be smaller than $V_{OL}$  ### Noise Margin Equations $NMH=V_{IL}-V_{OL} \approxeq V_{th,N}$ $NML=V_{OH}-V_{IH} \approxeq |V_{th,P}|$ Normally not worth the effort to calculate these precisely. ### Observations of Noise Margin $V_{OH}$ is quite close to the supply, while $V_{IH}$ has a larger distance to the power supply than the p threshold voltage. That means you get pretty good noise margin even with this simple definition. [^1] --- # References [^1]: [vr-4602-wk08-sc01-cmosvtc](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W8/vr-4602-wk08-sc01-cmosvtc.mp4)