2022-09-25 16:06 Status: # Design Flow ## Abstraction Need to think about abstraction level - everything is a model of the manufacture.  ### Lowest Level: Layout Know the interconnection, parasitics - transistors, drain areas, perimters, - length of interconnecting wires Most detailed representation of the chip. ## One level up: Schematic Image representation - don't know all parasitics as the wires are abstracted away. Analogue design done at this level. ## Next level up: Gate/Component Level Don't care about voltages/currents but logic/analogue function. ## Blocks Where we typically do digital design. - HDL: VHDL/Verilog - Gate level handled by the tools. ## System Level Complicated blocks - put down as a block without first designing it. ## Design Flow Tools ### Analogue - Schematic Entry - SPICE - Layout - Circuit Extraction - hopefully what you want to implement - Parasitic Extraction - Layer vs. Schematic (LVS) verification - Post layout simulation - HDL model (verilog A or AHDL) - Floorplanning (fit the circuits on the chip) ### Digital - Source: VDHL/Verilog model of the function - Digital Synthesis - turns model into gates - Gate level (Register transfer level) sims - Standard cells (key logic functions - AND,OR,XOR,flipflops) - Place & Route - Parasitic Extraction (gate delays) - interconnects determine time for nm tech so normally combined with place and route (expensive!!!) - Postlayout simulation - Floorplanning  Need transistor models for the spice sims. [^1] --- # References [^1]: [vr-4602-wk02-sc06-designflow](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W2/vr-4602-wk02-sc06-designflow.mp4)