2022-10-30 17:44
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# DAC and ADC Metrics
For ADCs and DACs we need a number of metrics to explain their behaviour.
## Digital-to-analogue Converter
$B_{in}=b_{N-1}\cdot\frac{1}{2}+b_{N-2}\cdot\frac{1}{4}+...+b_{0}\cdot\frac{1}{2^N}$ (where $b_0$ is the least significant bit (LSB)).
$V_{out} = B_{in}\cdot V_{ref}$ or $I_{out} = B_{in}\cdot I_{ref}$.
$0V < V_{out} < (1-\frac{1}{2^N})V_{ref}$
$V_{LSB} = \frac{V_{ref}}{2^N}$
### Signed representation - Two's Complement
$B_{in, complement}=b_{N-1}\cdot(-\frac{1}{2})+b_{N-2}\cdot\frac{1}{4}+...+b_{0}\cdot\frac{1}{2^N}$
This range then becomes minus half the reference to one LSB less than half the reference
$-\frac{1}{2}V_{ref}<V_{out}<(\frac{1}{2}-\frac{1}{2^N})V_{ref}$
## Analogue to Digital Converter
$0V \leq V_{in} < V_{ref}$
$B_{out}=b_{N-1}\cdot\frac{1}{2}+b_{N-2}\cdot\frac{1}{4}+...+b_{0}\cdot\frac{1}{2^N}$
For proper conversion, the output binary number must be chosen such that $B_{ref}\cdot V_{ref}=V_{in}+V_X$ where the error voltage $V_X$ is in the range $-\frac{1}{2}V_{LSB}\leq V_X\leq\frac{1}{2}V_{LSB}$.
The transistion point chosen here will have zero offset (desirable). We want the proportional line to go through the middle of all the levels.
## Converter Non-idealities
Ideally the transfer function should be a straight line (when we zoom out far enough that we can't see the levels).
### Gain Error
Angle of slope is not 45 degrees.
Often doesn't matter because many systems have unknown gain in their signal processing path.
### Offset Error
Often these are not important!
Offset doesn't matter because we are using AC signals so the DC value or the offset doesn't matter.
## Non-linearity
Always important!
### [Integral non-linearity](integral%20non-linearity.md)
The [integral non-linearity](integral%20non-linearity.md) is measured in LSB's.
e.g. a DAC would have an [INL](integral%20non-linearity.md) of $V_{max}/V_{LSB}$.
#### Zoomed in view of [INL](integral%20non-linearity.md) (fine grain)
Ideal spacing is one $V_{LSB}$.
Leads to the [Differential Non-linearity](#Differential%20Non-linearity)
### Differential Non-linearity
see [Differential Non-linearity](Differential%20Non-linearity.md)
Gives an idea of the difference per datapoint.
## Dynamic Properties
### ADC
Conversion Time = $1/f_{sample}$
### DAC
Settling Time (typically high precision)
Time from input change to settling within 1/2 an LSB
Worst case is for a [[Full Scale Range (FSR) Change]].
0000 -> 1111
Assume settling is a first order LPF ($V_{ref}\cdot e^{-\frac{t}{\tau}}$)
$V_{err}=\frac{1}{4} V_{LSB}$ implies $e^{-\frac{t}{\tau}}=2^{-N-2}$, so $t_{settle}=\tau\cdot(N+2)\cdot ln(2)$
So more bits means we will need to wait longer for it to settle.
[^1]
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# References
[^1]: [vr-4602-wk06-sc06-dacadcmetrics](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W7/vr-4602-wk06-sc06-dacadcmetrics.mp4)