2022-10-28 17:31 Status: # Continuous time comparators Often differential input. Output regarded as a digital logic function.  Simplest implementation: open loop op amp without compensation (slows down the circuit and not even needed!). ## Example: 16 bit audio, 44kHz sampling. [Successive approximation ADC](Successive%20approximation%20ADC.md): 17 clocks, so time to process one bit of $t_{bit} = (17\cdot44kHz)^-1$, thus producing a $17\cdot44kHz = 748kHz$ bandwidth. Would need a comparator within half a bit resolution - thus requiring a gain of $\geq 2^{17} = 102 dB$ and the $Gain\cdot Bandwidth = 98GHz$ which is huge for a conventional 16 bit audio signal. Op amps just wouldn't have the speed. ## Comparator  Common to put a buffer stage - digital inverter "buffer" (gives you gain and the only capacitance comes from the inverter therefore it is faster). You can have as many gain stages as you like and as high gain as you desire because you aren't using in feedback (no stability issues). PMOS differential or NMOS [differential pair](Differential%20Pair.md).  Consider input level range to decide on [differential pair](Differential%20Pair.md) type. ### Biasing Output of analogue stage needs to be in the transition region of the digital inverter in the bias condition. e.g. 1.8V PS, $v_{o2, bias} \approxeq 0.9V$ but this would be quite skewed if the digital has a 1.2V supply. Solution: Could put a source follower to drop the voltage by 0.5V.  This is process dependent! [^1] --- # References [^1]: [vr-4602-wk05-sc05-ctcomp](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W5/vr-4602-wk05-sc05-ctcomp.mp4)