2022-11-01 08:54 Tags: # Charge Scaling DAC Capacitors are usually preferable over resistors because the opamps driving capacitors don't need to drive a static current (makes opamp design easier). ## Charge Redistribution DAC Binary weighted set of capacitors  Since capacitors need their initial conditions set, we can't just use it like the [Binary Resistor Based DACs](Binary%20Resistor%20Based%20DACs.md) or [Current Scaling DACs](Current%20Scaling%20DACs.md). There needs to be a [Reset Phase](#Reset%20Phase). ### Reset Phase All the control switches are set to ref.  $B_n=0\ and\ R=1$ Reset switch is engaged - we have 0V at the sunmming node.Also 0V across feedback capacitor. Reference voltage is across all the capacitors. ### Use Phase $B_n=x\ and\ R=0$ When a bit is engaged, we would need to have a charge flowing from the output, through the feedback cap and through the cap to ground. Example: MSN changes  $Q=V_{ref}\cdot C_{MSB}$ which will cause a voltage drop across the feedback cap of $V_{out}=\frac{Q_{feedback}}{C_{feedback}} = \frac{V_{ref}\cdot C}{2C} = \frac{V_{ref}}{2}$Similarly, for the next bit the charge would be half that of the MSB (cap is half the size) which would produce a voltage drop of 1/2 a contribution of the reference voltage. Thus $V_{out} = \sum_{n=0}^{N-1}\frac{V_{ref}}{2^N}\cdot 2^n\cdot B_n$ ### Advantages - Very easy to make a signed converter! All that is needed is to change the definition of a 1 and 0 on the MSB switch. If reset phase set the MSB to ground, we will have 0V initial conditions. Setting it by setting the switch to $V_{ref}$ will cause charge to flow in the opposite direction and subtract from the final output. ## Variations Since we have a reset phase, it is a good idea to cancel the buffer op-amp offset. ### Circuit topology  Connect the output side of the feedback capacitor to ground instead of the output. We will then sample the offset voltage across the feedback capacitor. When we then connect the output voltage to the feedback cap the offset voltages will cancel. NB: You should do a more rigorous clock sequence so any charge injection from the feedback transistor switch can be cancelled and so that you O/C the grounded side of the capacitor before closing the feedback with the capacitor. ### Attenuation Capacitor  Series cap inserted into the ladder. This means the charge flowing into the cap will be different than the weight suggests. This lets you have less difference in size between smallest and largest capacitors. Ratio is reduced from $2^N$ to $2^{N/2}$ for the LS capacitors. ### Explanation If the attenuation cap is the same size as the LS capacitor, the most significant part of the LS array (very wordy, essentially the largest bit that after the series cap) with a value of C has half the total capacitance seen in the node 1:  #### MS bit of LS array (MS-LS array) Since node 2 is held at virtual ground, when the voltage changes (0v to $V_{ref}$) on the MS-LS array bit you will see half the voltage change on node 1. $\frac{V_{ref}}{2}$ across the LS cap will produce half the charge. Thus MS-LS charge change will produce half the charge of the LS-MS array cap (as it should). ### Disadvantages This is almost a C-2C ladder however you don't use C-2C because it is sensitive to stray capacitance on node 1 which may cause non-linearity. There is usually only 1 division of the array to reduce the ratio between smallest and largest capacitor in this converter. Stray capacitance on node 2 doesn't matter because it is held at virtual ground (so no charge will flow).  [^1] --- # References [^1]: [vr-4602-wk07-sc04-dacqscale](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W7/vr-4602-wk07-sc04-dacqscale.mp4)