2022-11-04 12:25 Tags: # CMOS Power Dissipation When CMOS gates are designed to minimise the crowbar current, the main power dissipation is due to the load capacitance. The load capacitance consists of: - Self loading of the gate - Input capacitance of whatever it drives (depends on fan out) - Wire capacitance of the line (depends on length width etc.) $C_L=C_{out}+C_{in}+C_{routing}$ ## Charging The power supply has to charge up the load capacitance.  $E_{DD}=\int_0^Tp(t)dt$ $=\int_0^TV_{DD}\cdot i(t)dt$ $E_{DD}=V_{DD}\cdot Q = V_{DD}^2\cdot C_L$ Now recall that the energy on the capacitor is only half this value ($E_{CL}=\frac{1}{2}C_LV_{DD}^2$) and so half the energy has been entirely lost in the charging process. We have also made no assumption of how this energy was delivered other than it wasn't stored anywhere and it comes from the positive power supply (so this power loss is fundamental!) ## Discharging Falling transition on the capacitor. The NMOS discharges the capacitor. All the energy stored in the capacitor is dissipated in the NMOS.  ## Output Switching at f Power consumed by the gate is frequency times energy per cycle $P=f\cdot E_{DD}=f\cdot C_L \cdot V_{DD}^2$ To minimise P: - prevent gates from switching unless they have to ($\downarrow f$) - Minimise the supply voltage ($\downarrow V_{DD}$) - Load capacitance depends on the transistor area ($\downarrow W\cdot L$ since $C_{D},C_{G} \propto W\cdot L$). See [Multi-Project Wafers (MPW)](Multi-Project%20Wafers%20(MPW).md) [^1] --- # References [^1]: [vr-4602-wk08-sc02-cmosswitching](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W8/vr-4602-wk08-sc02-cmosswitching.mp4)