2022-09-25 18:03
Status:
# Analogue Tools
Important to be disciplined.
## Schematic Entry
### Use a good heirarchy:
- functional breakdown
- reflected in layout
### Cell schematic:
- Use physical components only!
e.g. simple amplifier:
- Good port names
- Don't use global names - include power rails (no connection to supply you didn't know you have) 
- **NEVER** put voltage sources for testing
- have a good symbol for the amplifier.
Very important to make sure this is correct!
### Test Bench
- Test sources
- Current sources - only ever used as input to current mirrors.
## Layout
- Cell layout
- pcells (premade)
- matching (symmetrical gives much better matching performance) -
## Distribution
- Power - wide enough for current (e.g. 1mA/$\mu m$)
- Clock
- arrives at same time at all the gates (equal delay)
- interference
- References distribution
- use shielding
## Pad Ring
Coming off the chip - on the perimeter.
Where you think about I/O buffering (off chip capacitances are larger, impedances are much lower - beef up signal).
[Electrostatic Discharge (ESD) Protection](Electrostatic%20Discharge%20(ESD)%20Protection.md)
## Routing
- Wire layer and width
- Port placement dictates how you can route to a cell - makes intercell routing easier
ex:
Ports at the boundary to route on same metal layer.
Metal 1 (blue) on left and right, metal 2 (pink) on top and bottom (typical).
Also lets you connect ports to itself across the chip - e.g. metal 3 (grey).
## SPICE Simulations
### Functional Simulations
Check it is performing the functions it was designed for.
- metrics used
- verify specs met
- Very important to simulate over as many variations as you can think of (large tolerances for manufacturing)
- Corner Simulations
- PVT
- Process variation (fast, slow, up, down)
- Power supply voltage
- Temperature
- References: V, I, f
- Monte-Carlo Simulations (matching - add random variations, very efficient to explore large amount of parameters to get statistics).
- Simulations on extracted netlist to see parasitic effects.
Factors - 
More parameters - higher dimensional 'rectangle'
Higher currents - run faster
On an inverter, up is the fast p - down is the fast pull down.
Hot temperatures - likely slow transistors - simulate hot temp in the slow corner to get extra slow corner.
More components - resistors, caps, inductors - add to sims *or* include in slow corner (large caps) or fast corner (small caps).
## Extraction
Verification extraction:
- Schematic components (transistors)
- Interconnections
Can also do parasitic extraction:
- capacitances
- Resistances:
Need to set a threshold or the parasitic netlist becomes too big.
Then proceed to postlayout simulation.
[^1]
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# References
[^1]: [vr-4602-wk02-sc07-analoguetools](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W2/vr-4602-wk02-sc07-analoguetools.mp4)