2022-11-01 10:37 Tags: # Algorithmic and Pipelined ADCs Use binary search to do the conversion. Sample and hold, comparator, multiply by 2 and adder. ## Algorithmic Converter ### Basic Circuit  ### Operation #### Words In the first clock, the input voltage is routed through the sample and hold. This is compared to half the reference voltage. Instead of changing what you compare against, you find the residue (if input is larger than half the reference, you subtract half the reference). Thus the rest of it is between 0 and $\frac{V_{ref}}{2}$. Multiply it by 2 and run it through again. Every time you get another bit out. #### Plot  ### Advantages - Very compact (simple) - Popular choice - Easy to [Process Signed Signals](#Processing%20Signed%20Signals) ### Disadvantages - Conversion time same as for successive approximation - N clock cycles for N bits ### Processing Signed Signals Minor change. Compare against GND instead of $\frac{V_{ref}}{2}$ and then add or subtract $\frac{V_{ref}}{4}$. ## Pipeline ADC One of the highest performance ADC's of typical use. Exactly the same structure as the [Algorithmic Converter](#Algorithmic%20Converter) however instead of feeding the residual voltage back to the sample and hold, we feed it into another identical structure:  ### Advantages - Very fast [throughput](../General/throughput.md)! Once the first structure has passed the residual voltage on, it is free to process another input signal. So it can process one input signal per clock. [Throughput](../General/throughput.md) is 1 sample per clock. ### Disadvantages - Latency is still N clocks, but this often doesn't matter. [^1] --- # References [^1]: [vr-4602-wk07-sc07-adcpipeline](../../Spaces/University/ELEC4602%20–%20Microelectronics%20Design%20and%20Technology/Lectures/W7/vr-4602-wk07-sc07-adcpipeline.mp4)